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Espressif Systems /ESP32-S3 /SPI0 /SRAM_CLK

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Interpret as SRAM_CLK

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SCLKCNT_L0SCLKCNT_H0SCLKCNT_N0 (SCLK_EQU_SYSCLK)SCLK_EQU_SYSCLK

Description

SPI_CLK clock division register when SPI0 accesses to Ext_RAM.

Fields

SCLKCNT_L

It must equal to the value of SPI_MEM_SCLKCNT_N.
SCLKCNT_H

It must be a floor value of ((SPI_MEM_SCLKCNT_N+1)/2-1).
SCLKCNT_N

When SPI0 accesses to Ext_RAM, f_SPI_CLK = f_MSPI_CORE_CLK/(SPI_MEM_SCLKCNT_N+1)
SCLK_EQU_SYSCLK

When SPI0 accesses to Ext_RAM, set this bit in 1-division mode, f_SPI_CLK = f_MSPI_CORE_CLK.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data